[PATCH v1 1/2] gnu: iverilog: Fix yosys tests
(address . guix-patches@gnu.org)(name . Jakob Kirsch)(address . jakob.kirsch@web.de)
* gnu/packages/fpga.scm (iverilog): [inputs]: Add zlib.
Change-Id: I961bf73b17f96a5891232a8646bc04581dfb8bfc
---
gnu/packages/fpga.scm | 1 +
1 file changed, 1 insertion(+)
Toggle diff (14 lines)
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 545ec3482d..153d17d1f3 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -125,6 +125,7 @@ (define-public iverilog
#:make-flags #~(list (string-append "PREFIX="
#$output))
#:bootstrap-scripts #~(list "autoconf.sh")))
+ (inputs (list zlib))
(native-inputs (list autoconf bison flex gperf))
(home-page "https://steveicarus.github.io/iverilog")
(synopsis "FPGA Verilog simulation and synthesis tool")
base-commit: 5703914e93d81ac6037240582abe899282e78f15
--
2.46.0