Here's a patch series that aims to improve the package for Yosys, a tool for
synthesizing Verilog RTL designs, by
- Updating the source-repository and home-page URLs to their current location;
- Updating the package definition to the modern style, using gexps and
- Having Yosys use the "abc" executable from Guix's package rather than
creating and installing a duplicate copy;
- Explicitly propagating packages with executables Yosys invokes at runtime
rather than embedding store references in Yosys' code; and
- Updating Yosys to version 0.24.
I've tested building the package and its dependencies on x86-64 and AArch64
and everything seems okay. Again, arachne-pnr fails to build in any case
and will need separate attention.
 Yosys' README.md file includes sample sessions useful for testing,
particularly whether external tools can be invoked via the "show" and
The files "fiedler-cooley.v" and "mycells.lib" are present in the source
Simon South (5):
gnu: yosys: Update source and home-page URLs.
gnu: yosys: Use new package style.
gnu: yosys: Use external abc.
gnu: yosys: Propagate external dependencies.
gnu: yosys: Update to 0.24.
gnu/packages/fpga.scm | 120 ++++++++++++++++--------------------------
1 file changed, 45 insertions(+), 75 deletions(-)