(address . guix-patches@gnu.org)
20220818231841.vncyowy57s2awb74@silvi
Hi!
I've stumbled upon this beautiful little piece of software that let's
you generate FFT designs in Verilog. Since it's free software I thought
I'd ready it up for my favorite distribution!
Thanks for merging!
gabriel
From 189ae40cb6104ac703f0171e32fe88208f9fcc25 Mon Sep 17 00:00:00 2001
From: Gabriel Wicki <gabriel@erlikon.ch>
Date: Fri, 19 Aug 2022 01:14:06 +0200
Subject: [PATCH] gnu: Add fftgen.
* gnu/packages/fpga.scm (fftgen): New variable.
---
gnu/packages/fpga.scm | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
Toggle diff (41 lines)
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 06d4a10e7e..e1ae577c65 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -552,3 +552,34 @@ (define-public verilator
performs the design simulation. Verilator also supports linking its generated
libraries, optionally encrypted, into other simulators.")
(license license:lgpl3)))
+
+(define-public fftgen
+ (let ((commit "1d75a992efd0528edea128a903aafdabe133cb08")
+ (revision "0"))
+ (package
+ (name "fftgen")
+ (version (git-version "0" revision commit))
+ (source (origin
+ (method git-fetch)
+ (uri (git-reference
+ (url "https://github.com/ZipCPU/dblclockfft")
+ (commit commit)))
+ (file-name (git-file-name name
+ (string-take commit 8)))
+ (sha256
+ (base32
+ "0qq874yalzpjdwnxhc5df8a0ifywv29wcncb09945x56xplvkcmd"))))
+ (build-system gnu-build-system)
+ (arguments
+ `(#:tests? #f
+ #:phases (modify-phases %standard-phases
+ (delete 'configure)
+ (replace 'install
+ (lambda* (#:key outputs #:allow-other-keys)
+ (let ((bin (string-append (assoc-ref outputs "out")
+ "/bin")))
+ (install-file "sw/fftgen" bin) #t))))))
+ (synopsis "Generic Pipelined FFT Core Generator")
+ (description "fftgen produces FFT hardware designs in Verilog.")
+ (home-page "https://zipcpu.com/")
+ (license license:lgpl3))))
--
2.36.1