New package: fftgen

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3 participants
  • Gabriel Wicki
  • Ludovic Courtès
  • Maxime Devos
Owner
unassigned
Submitted by
Gabriel Wicki
Severity
normal
G
G
Gabriel Wicki wrote on 19 Aug 2022 01:18
(address . guix-patches@gnu.org)
20220818231841.vncyowy57s2awb74@silvi
Hi!

I've stumbled upon this beautiful little piece of software that let's
you generate FFT designs in Verilog. Since it's free software I thought
I'd ready it up for my favorite distribution!

Thanks for merging!

gabriel


From 189ae40cb6104ac703f0171e32fe88208f9fcc25 Mon Sep 17 00:00:00 2001
From: Gabriel Wicki <gabriel@erlikon.ch>
Date: Fri, 19 Aug 2022 01:14:06 +0200
Subject: [PATCH] gnu: Add fftgen.

* gnu/packages/fpga.scm (fftgen): New variable.
---
gnu/packages/fpga.scm | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)

Toggle diff (41 lines)
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 06d4a10e7e..e1ae577c65 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -552,3 +552,34 @@ (define-public verilator
performs the design simulation. Verilator also supports linking its generated
libraries, optionally encrypted, into other simulators.")
(license license:lgpl3)))
+
+(define-public fftgen
+ (let ((commit "1d75a992efd0528edea128a903aafdabe133cb08")
+ (revision "0"))
+ (package
+ (name "fftgen")
+ (version (git-version "0" revision commit))
+ (source (origin
+ (method git-fetch)
+ (uri (git-reference
+ (url "https://github.com/ZipCPU/dblclockfft")
+ (commit commit)))
+ (file-name (git-file-name name
+ (string-take commit 8)))
+ (sha256
+ (base32
+ "0qq874yalzpjdwnxhc5df8a0ifywv29wcncb09945x56xplvkcmd"))))
+ (build-system gnu-build-system)
+ (arguments
+ `(#:tests? #f
+ #:phases (modify-phases %standard-phases
+ (delete 'configure)
+ (replace 'install
+ (lambda* (#:key outputs #:allow-other-keys)
+ (let ((bin (string-append (assoc-ref outputs "out")
+ "/bin")))
+ (install-file "sw/fftgen" bin) #t))))))
+ (synopsis "Generic Pipelined FFT Core Generator")
+ (description "fftgen produces FFT hardware designs in Verilog.")
+ (home-page "https://zipcpu.com/")
+ (license license:lgpl3))))
--
2.36.1
L
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Ludovic Courtès wrote on 2 Sep 2022 17:29
(name . Gabriel Wicki)(address . gabriel@erlikon.ch)(address . 57291-done@debbugs.gnu.org)
87zgfhu74i.fsf@gnu.org
Hi,

Gabriel Wicki <gabriel@erlikon.ch> skribis:

Toggle quote (7 lines)
>>From 189ae40cb6104ac703f0171e32fe88208f9fcc25 Mon Sep 17 00:00:00 2001
> From: Gabriel Wicki <gabriel@erlikon.ch>
> Date: Fri, 19 Aug 2022 01:14:06 +0200
> Subject: [PATCH] gnu: Add fftgen.
>
> * gnu/packages/fpga.scm (fftgen): New variable.

Applied with the minor changes below, thanks!

Ludo’.
Toggle diff (44 lines)
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index e1ae577c65..58b81bf83a 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -554,7 +554,7 @@ (define-public verilator
(license license:lgpl3)))
(define-public fftgen
- (let ((commit "1d75a992efd0528edea128a903aafdabe133cb08")
+ (let ((commit "1d75a992efd0528edea128a903aafdabe133cb08") ;no releases
(revision "0"))
(package
(name "fftgen")
@@ -564,22 +564,23 @@ (define-public fftgen
(uri (git-reference
(url "https://github.com/ZipCPU/dblclockfft")
(commit commit)))
- (file-name (git-file-name name
- (string-take commit 8)))
+ (file-name (git-file-name name version))
(sha256
(base32
"0qq874yalzpjdwnxhc5df8a0ifywv29wcncb09945x56xplvkcmd"))))
(build-system gnu-build-system)
(arguments
- `(#:tests? #f
+ `(#:tests? #f ;no tests
+ #:make-flags '("CFLAGS=-g -O2") ;default flags lack -O2
#:phases (modify-phases %standard-phases
(delete 'configure)
(replace 'install
(lambda* (#:key outputs #:allow-other-keys)
(let ((bin (string-append (assoc-ref outputs "out")
"/bin")))
- (install-file "sw/fftgen" bin) #t))))))
- (synopsis "Generic Pipelined FFT Core Generator")
- (description "fftgen produces FFT hardware designs in Verilog.")
+ (install-file "sw/fftgen" bin)))))))
+ (synopsis "Generic pipelined FFT core generator")
+ (description "fftgen produces @acronym{FFT, fast-Fourier transforms}
+hardware designs in Verilog.")
(home-page "https://zipcpu.com/")
- (license license:lgpl3))))
+ (license license:lgpl3+))))
Closed
M
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Maxime Devos wrote on 2 Sep 2022 20:57
Re: [bug#57291] New package: fftgen
00f0e2ce-7286-6be8-d807-15703fe9778a@telenet.be
On 19-08-2022 01:18, Gabriel Wicki wrote:
Toggle quote (2 lines)
> + (file-name (git-file-name name
> + (string-take commit 8)))
You don't have to string-take, the standard pattern is (git-file-name
name version), as in (guix)Version Numbers.
Toggle quote (1 lines)
> + `(#:tests? #f
Why are tests disabled?  There is a bench-test target, maybe you need
#:test-target "bench-test"? I hope that means "test bench" and not
"benchmark" though.
On the license: some parts are GPL3+ (see:
sounds important to add to the license field to me (license
(license:lgpl3+ license:gpl3+)).
Greetings,
Maxime.
Attachment: OpenPGP_signature
M
M
Maxime Devos wrote on 2 Sep 2022 21:00
Re: bug#57291: New package: fftgen
21feec52-1ffd-59c1-60fb-e99fb1ae86d8@telenet.be
On 02-09-2022 17:29, Ludovic Courtès wrote:
Toggle quote (1 lines)
> + #:make-flags '("CFLAGS=-g -O2") ;default flags lack -O2
I think (string-append "CXX=" #$(cxx-for-target)) is needed to, for
cross-compilation.
Greetings,
Maxime.
Attachment: OpenPGP_signature
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